behavioural Architecture Reference

Processes
release_process	( tb_clk , tb_rst , end_of_file )
	flowchart: release_process [Release process]
reading_input_pixels	( tb_clk )
writing_output_file	( tb_clk )
h_and_v_counters	( tb_clk )

Signals
tb_clk	std_logic := ' 0 '
tb_rst	std_logic := ' 0 '
tb_enable	std_logic := ' 0 '
tb_done	std_logic := ' 0 '
dut_data_valid	std_logic := ' 0 '
end_of_file	std_logic := ' 0 '
pixel_tmp	std_logic_vector ( wordsize - 1 downto 0 ) := ( others = > ' 0 ' )

Files
file_input_pixel	text open read_mode is input_file
	File containing pixels for input of the testbench.
file_output_pixel	text open write_mode is output_file
	File used as output for the tesbench.

Member Function Documentation

h_and_v_counters()

h_and_v_counters (   tb_clk   )

Process

reading_input_pixels()

reading_input_pixels (   tb_clk   )

Process

release_process()

release_process (   tb_clk ,   tb_rst ,   end_of_file   )

Process

flowchart: release_process
[Release process]

writing_output_file()

writing_output_file (   tb_clk   )

Process

Member Data Documentation

dut_data_valid

dut_data_valid std_logic := ' 0 '

Signal

end_of_file

end_of_file std_logic := ' 0 '

Signal

file_input_pixel

file_input_pixel text open read_mode is input_file

File

File containing pixels for input of the testbench.

file_output_pixel

file_output_pixel text open write_mode is output_file

File

File used as output for the tesbench.

pixel_tmp

pixel_tmp std_logic_vector ( wordsize - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

tb_clk

tb_clk std_logic := ' 0 '

Signal

tb_done

tb_done std_logic := ' 0 '

Signal

tb_enable

tb_enable std_logic := ' 0 '

Signal

tb_rst

tb_rst std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• /home/ben/Programming/VHDL/realtimestagram/src/testbench_drivers/src/test_bench_driver.vhd