structural Architecture Reference

Components
test_bench_driver	<Entity test_bench_driver>
vignette	<Entity vignette>

Signals
clk	std_logic := ' 0 '
rst	std_logic := ' 0 '
enable	std_logic := ' 0 '
h_count	std_logic_vector ( ( integer ( ceil ( log2 ( real ( image_width ) ) ) ) - 1 ) downto 0 ) := ( others = > ' 0 ' )
v_count	std_logic_vector ( ( integer ( ceil ( log2 ( real ( image_height ) ) ) ) - 1 ) downto 0 ) := ( others = > ' 0 ' )
pixel_from_file	std_logic_vector ( ( const_wordsize - 1 ) downto 0 ) := ( others = > ' 0 ' )
pixel_to_file	std_logic_vector ( ( const_wordsize - 1 ) downto 0 ) := ( others = > ' 0 ' )

Instantiations
tst_driver	test_bench_driver <Entity test_bench_driver>
device_under_test	vignette <Entity vignette>

Member Data Documentation

clk

clk std_logic := ' 0 '

Signal

device_under_test

device_under_test vignette

Instantiation

enable

enable std_logic := ' 0 '

Signal

h_count

h_count std_logic_vector ( ( integer ( ceil ( log2 ( real ( image_width ) ) ) ) - 1 ) downto 0 ) := ( others = > ' 0 ' )

Signal

pixel_from_file

pixel_from_file std_logic_vector ( ( const_wordsize - 1 ) downto 0 ) := ( others = > ' 0 ' )

Signal

pixel_to_file

pixel_to_file std_logic_vector ( ( const_wordsize - 1 ) downto 0 ) := ( others = > ' 0 ' )

Signal

rst

rst std_logic := ' 0 '

Signal

test_bench_driver

test_bench_driver

Component

tst_driver

tst_driver test_bench_driver

Instantiation

v_count

v_count std_logic_vector ( ( integer ( ceil ( log2 ( real ( image_height ) ) ) ) - 1 ) downto 0 ) := ( others = > ' 0 ' )

Signal

vignette

vignette

Component

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The documentation for this class was generated from the following file:

• /home/ben/Programming/VHDL/realtimestagram/src/lut/tst/vignette_tb.vhd